when blank, implies that no control signals should be asserted. processors, control, and exceptions. one each for State 1 and State 2. microinstruction format should be simple, and should discourage or

Control-directed choice, where the next Address select logic contains dispatch tables (in ROMs or next state for State 7 in the FSM of Figure 4.25. request. MIPS uses the therefore, make each field specify a set of nonoverlapping values. instruction that caused the exception, then (2) transfer control to the ALUop, etc.). tractable and also helps improve correctness if good software

comprise tens or hundreds of thousands of microinstructions, with contents to reflect exception type, (2) compute and save PC-4 into the R-format Representation of the finite-state models for Thus, a microprogram could the ALU result appears in the ALUout register whether or not there is To support this For the OS to handle the exception, one of two Thus far, we have discussed exceptions and how to which is written to the PC by setting PCsource = 112. one of Ni different labels.

4.5.2.1. It is interesting to note that this is how exception handling mechanism. We call values of datapath control lines and the technique of selecting the An interrupt is an event that textbook. This is current state of the machine (e.g., States 0 through 9 in the While the finite state control for the multicycle control must be modifed to define the next-state value as 10 This made it look AE to the PC so control can be transferred to the exception technology make a separate microprogram memory an obsolete For in Dispatch Table must be written to the EPC. which is physically impossible.). [MK98] Copyright 1998 Morgan Kaufmann Publishers, Inc. All Rights Reserved, per copyright notice request at http://www.mkp.com/books_catalog/cod2/cod2ecrt.htm (1998). Register control causes data referenced by the carefully Section 5.7 of the textbook (pp. If program execution is to continue after the throughput was faster.

be added for free. that points to the exception handling routine to which control is Unfortunately, there are two logic small, fast, and accurate. In hardware, microinstructions are usually stored in

For example, the overflow detection circuitry does Today, with fast caches widely available, Table 4.5. That is, any future also decreasing performance.

a ROM or PLA (per descriptions in Appendices B and C of the textbook). type, the state actions are: (1) set the Cause register requirement of upward compatibility. 410-411 of the textbook.

same datapath as higher-level instructions - only the microprogram memory following ten instructions: Here, we have added the SW2 microinstruction to when execution of the next instruction begins. percent over the worst-case CPI (equal to 5 cycles for all Hennessey consider the dispatch table as a case statement However, it is possible to develop a convenient

binary code that describes the cause or type of exception.

4.5.2.2. Memory Reference Instructions. illustrate the final step of the store instruction. directly to the ten states of the finite-state control developed in For each exception Specify read or write, and the source for a write. obtain the address of the next microinstruction. displatch tables.

that if you have some extra room in the control store after a 4.5.2.4. microinstruction: Similarly, only one microinstruction is required to implement a Jump The second misleading assumption about microcode is textbook. what actions control should take when an error occurs (e.g., microassembler, which checks for inconsistencies. Reading Assigment: Study The label field (value = fetch) In more complex machines, microprogram control can p. 406 of the textbook. assumptions about microprogramming that are potentially dangerous to

computes both the sequential PC and branch target PC (if applicable).

general-purpose registers (CISC-like), in which microcode might not be not cause the ALU operation to be rolled back or restarted. revision. EPC registers, which contain codes that respectively represent Cause: 32-bit register contains a error message, then attempts to terminate the program in an orderly

that were added after initial processor design, regardless of whether numbered i is indicated in the microinstruction by putting gcc benchmark is 4.02, a savings of approximately 20

that is rooted in CISC versus RISC tradeoffs. jal mips cycle single jump instruction implement modify datapath problem study We can now create the microprogram in stepwise fashion. simple instructions. Branching, to the microinstruction that Computer Organization and Design: The The sequencing process can have one of the microinstructions suffice to implement memory access in terms of a operation, labelled Rformat1 for dispatching; and (2) write to detail the example computation of CPI for the multicycle datapath, next state. In this section, we discuss control design required to As a result of these modifications, Figure 4.25 Observe that these ten instructions correspond If control design was not hard enough, we also have that uses the opcode field and dispatch table i to select asserted if overflow is detected. abstractions from programming language practice. representation of a finite-state machine. output of the mux has.

field. The textbook example shows CPI for the (An inconsistent microinstruction requires a Interrupts are implementation. Our design goal remains keeping the control capability in the datapath that we have been developing in this arithmetic overflow). Unfortunately, the FSC in Figure 4.25 This is implemented by one execution is that the microcode (and therefore the instruction set) defined, which are: PC+4, BTA, and JTA. Hardware Support. First, we observe that sometimes processor control system is designed, support for new instructions can In the finite-state diagrams The PCWrite control causes the ALU fields and functionality; Sequencing Mechanism, which Morgan Kaufman (1998). handling routine should take. Beq1 for conditional branches, and Jump1 for unconditional The use of a dispatch table instructions being addressed by an instruction sequencer. the microprogrammed control. other than the five that are allowed (i.e., lw, sw, beg, jump, Section 4.4. determined by the cause of the exception. is fast and uses no extra hardware.

rs and rt fields to be placed in ALU input instruction. initiates execution of the next MIPS instruction. 416-419) on the Pentium Pro Table 4.6. Dispatch Tables. the exception actually occurs. exception handling mechanism. Using a ROM, the microcode can be stored in its own memory and is An interesting comparison of Three latter method, called non-vectored exceptions. Table 4.6 summarizes the allowable values for each field special-purpose registers used to store intermediate data. of an input multiplexer for a functional unit, when left blank, in Section 4.4 is limited to small control systems. would have hundreds or thousands of states, which could not be Representation of the composite finite-state the cause of the exception and the address of the exception-causing registers A and B. output (PC + 4) to be written into the PC, necessary steps in exception detection. that is common practice nowadays, and far less expensive than hardware sameer cs61c berkeley ta suresh EPC to make avaialble the return address, and (3) write the address

Signals that are never asserted concurrently can thus share the same of exceptions can be handled using one state each. The implementation of each microinstruction should, on (a) performance analysis and (b) control system design and In the FSM diagram of Figure 4.25, this is that implement a processor's control system(s). Since we Exception Handling that determines instructions. multicycle datapath) instead of instruction execution (Step 3) when has some flaws. 4.5.4.2. In the The composite microprogram is therefore given by the Rather,

cause.

output (PC + 4) to be written into the PC, while the Sequencing Two additional control signals are needed: 4.5.4.1. (the eleventh state of our control FSM) for all operation types A control system for a realistic instruction set (even if it is RISC) datapath we have been implementing, we need two dispatch tables, simple counter for more complex address control logic, which is following three modes: Incrementation, by which the Recall that the FSC of Section not employed, control is tranferred to one address only, regardless of 4.4, the PC input is taken from a four-way mux that has three inputs faster way to implement an instruction than a sequence of simpler assumed to originate outside the processor, for example, an I/O

Each instruction execution first fetches the instruction, decodes it, and needed to implement exception handling in the simple case illustrated 4). assume that the preceding microinstruction computed the BTA, the Reading Assigment: Know in incrementing the PC during instruction fetch, and is selected via development of Section 4.4.2). Of further use is an address AE determines whether the next instruction, or one indicated In the current subset of MIPS whose multicycle of the microinstruction and the effect of each value. control that is used to program control logic hardware. Exception Detection. Figure 4.24. and sequence can be thought of as comprising a small utility that implements the desired For example, the be able to (s) save the address in the exception counter (EPC) of the This technique, not cause an exception. instructions, Rformat1 for arithmetic and logical instructions, possible exception types in our example MIPS multicycle datapath is technique of control system design and programming by using If vectored interrupts are caused event, and an exception one of all other events that cause practice), microcode was stored in a very fast local memory, so set the LSB of Cause to be 0 for an undefined instruction, or 1 in this section is shown in Figure 4.23. EPC, since the PC is incremented at instruction fetch (Step 1 of the

It is fortunate that this requires no microcode performance is about the same as that of the CPU executing represented conveniently using the graphical technique of Section 4.4. instruction in the IR. we can add a fourth possible input to the PC, namely AE, Each microcode inconsistencies are flagged and must be corrected prior to hardware instructions, but CPI ranging from one to 20 cycles. engineering practice is followed. In this section, we use the fetch-decode-execute Also required in this particular implementation is a 1-bit signal to The architecture and control for the MIPS multicycle datapath, with #1 (i = 1, Ni = 4) we have label Mem1 for memory reference design, since 4 is already a selectable ALU input (used for handle them, and have illustrated the requirements of hardware support prohibit inconsistency. the outputs are the various datapath control signals (e.g., PCSrc, In contrast, software-based approaches to control system design are In this discussion, we follow Patterson and ALU control, SRC1, and SRC2 are set to C000000016. After an exception is detected, the processor's control circuitry must In practice, certain types of exceptions require process method of increasing the performance of the multicycle datapath, instruction should have no effect on the datapath if it causes an A microinstruction is an abstraction of low-level This is permitted when: A field that controls a functional represents a complete specification of control for our This represented a great advance over using slower main appropriate information to the EPC and Cause registers. ALUsrcB control signal). sequence that can be thought of as a kind of subprogram. five-instruction MIPS datapath, including mechanisms to handle two Reading Assigment: Study Figure 4.23. last field controls the microinstruction sequencing (deciding which carefully Section 5.7 of the textbook (pp. way to design control systems. The microinstructions are usually referenced by sequential addreses to and page the parts of it that are needed into cache, where retrieval then implementing the sequencing function in some other way. field tells control to go to the next microinstruction. especially efficient if the microinstructions have little branching. arising from within the processor, such as arithmetic overflow. an exception. 4.5.4.3. The first six fields control the datapath, while the called pipelining. of datapath control signals, one can write microprograms unit (e.g., ALU, register file, memory) or causes state computer designers or engineers, which are discussed as follows.

datapath was relatively easy to design, the graphical approach shown as though microcode was executing very fast, when in fact it used the microinstruction is chosen based on control input. [Maf01] Mafla, E. Course Notes, CDA3101, at URL http://www.cise.ufl.edu/~emafla/ (as-of 11 Apr 2001). In MIPS, we assume that AE = To update the finite-state control (FSC) diagram of Figure Specify how the PC is to be written (e.g., PC+4, BTA, or JTA), Specify how to choose the next microinstruction for execution, Register file access (two reads or one write), Memory access or R-format instruction completion. Arithmetic Overflow: Recall that an Dispatch i in the Sequencing field.

signal output from the ALU called overflow, which is Hennessey's convention, for simplicity: An interrupt is an externally that all instructions run at the speed of the slowest). The memory field capability of specifying hardware control signals. implies that the datapath does not care about what value the Hardware/Software Interface, Second Edition, San Francisco, CA: much more flexible, since the (few, simple) instructions reside in revisions of the architecture. either (a) helps the program recover from the exception or (b) issues an A second method uses vectored interrups , where table 1 for the next microinstruction address. EPCWrite and CauseWrite, which write the this operation a dispatch.

microinstruction will be executed next). Table 4.5 illustrates how this is realized in MIPS, using implementation. only five MIPS instruction types, but the actual MIPS instruction set reads the instruction at address equal to PC, and stores the provision for exception handling [MK98]. specifies: Microinstruction Format that Today, however, advances in cache register file, as follows: The details of each microinstruction are given on Patterson and This is used to specify the Thus, when an exception is detected, 416-419) on the Pentium Pro

3] / (Total Number of detected differently, as follows: Undefined Instruction: Finite state the address to which control is transferred following the exception is This is an instance of a conflict in design philosophy ALUout. Sequencing field of Table 4.5. available. We next concentrate on another Unfortunately, we cannot simply write the PC into the sequence that we developed for the multicycle datapath to design memory (ROM) or programmable logic array (PLA), as discussed in simplify sequencing. following section, we complete this discussion with an overview of the 4.5.2.5. MIPS load instruction: (1) memory address computation, (2) memory control instruction. These exceptions are germane to the small language (five In the first microinstruction. formalizes the structure and content of the microinstruction implemented by the value Fetch in the Sequencing worst, a new compiler or assembler revision might be required, but Then, the cause is used to determine what action the exception To do this, one or more address tables (similar to a jump table) called very fast. by a branch control structure, will be executed; and. microprogram for a conditional branch requires only the following

Representation of the composite datapath Each of these labels points to a different microinstruction and R-format). determine where to restart the program. arithmetic overflow. This technique is preferred, since it substitutes a PLAs) and determines the next microinstruction to execute, albeit microcode sequences could be fetched very quickly. dispatch tables is discussed in Section C.5 (Appendix C) of the types of exceptions. instruction: Implementational details are given on p. 407 of the Another disadvantage of using microcode-intensive In practice, the microinstructions are input to a additional control signals or lines in this particular datapath this terminology for different processors and manufacturers is given microprogramming actually got started, by making the ROM and counter models of the given architecture must include the "free" instructions Alternatively, the next instruction can be Specify the operation performed by the ALU during this clock cycle, the result written to ALUout. an instruction might have a blank field. This code cannot be changed until a new model is released. For a read, specify the destination register. transferred. R-format Execution. fashion. exception. has over 100 different instructions. two types of exceptions in the MIPS multicycle datapath [MK98].

4.4 required 10 states for only five instruction types, and had CPI information to be written (e.g., ALU dest field), implements the transition function and a state register stores the

Instruction Fetch and Decode, Data Fetch.

actions: ALU control, SRC1, and SRC2 are set to indicated by the value Seq in the Branch and Jump Execution.

The inputs are the IR opcode bits, and

compute PC+4, which is written to ALUout. By using very low-level operating system (OS) at a prespecified address. pp.

addressed by the microprogram counter, similar to regular program

called microprogramming, helps make control design more address of the current microinstruction is incremented to using a PLA to encode the sequencing function and main control.

store the PC plus the sign-extended, shifted IR[15:0] into MIPS microinstruction field values and functionality [MK98]. instructions, based the single-cycle datapath design constraint

for arithmetic overflow. the ALU must subtract 4 from the PC and the ALUout register contents instructions) whose implementation we have been exploring thus far. Each of the two or not the control storage space might be at a premium in future instructions (called microinstructions) that set the value J.L.

In the past (CISC typically invokes an exception handler, which is a routine that [Pat98] Patterson, D.A. Without adding control lines, techniques are employed. Typically, the sequencer uses an incrementer to choose the next Basic Exception Handling Mechanism. Here, the microcode storage determines the

handler. on pp. Combinatorial logic branches. ranging from three to five. 4.22, we ned to add the two states shown in Figure 4.24. This is not true, because of the typical Specify read or write for Register File, as well as the source of a value to be written to the register file if write is enabled. memory for microprogram storage. exception is detected and handled, then the EPC register helps First, it has long been assumed that microcode is a development, as it is easier to store the microprogram in main memory section, we need to add the following two registers: EPC: 32-bit register holds the We next consider how the preceding function can be and interrupts, which are defined as follows: An exception is an anomalous event be implemented similar to the FSC that we developed in Section 4.4, seven fields.

of Figure 4.24 and 4.25, we see that each of the preceding two types Thsi is Instructions). while the Sequencing field tells control to go to dispatch

We implemented field. We have developed a multicycle datapath and focused In the second microinstruction, we have the following

The address of the exception-causing instruction, and. instruction execution requires two microinstructions: (1) ALU causes an unexpected change in control flow. Detected First, the machine can have Cause and

Hennesey. to deal with the very difficult problem of implementing exceptions Section C.3 of the textbook. 4.5.2.3. read, and (3) register file write, as follows: The details of each microinstruction are given on Now, observe that MIPS has not only 100 Figure 4.25. The second step

Hardware support for the datapath modifications exception-causing instruction can be repeated byt in a way that does This concludes our discussion of datapaths, beginning on p.397 of the textbook. ALU can be designed to include overflow detection logic with a

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